Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)


  • Muhammad Irfan Universitas Islam Indonesia, Daerah Istimewa Yogyakarta
  • Hendra Setiawan Universitas Islam Indonesia, Daerah Istimewa Yogyakarta



Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat. Field Programmable Gate Array (FPGA) merupakan salah satu perangkat yang dapat digunakan untuk implementasi komputasi yang memerlukan kecepatan dan presisi tinggi. Penerapan komputasi akar kuadrat pada FPGA menggunakan metode digit by digit non-restoring dengan beberapa modifikasi agar memiliki hasil perhitungan dengan nilai error yang kecil. Sistem tersebut diimplementasikan menggunakan 32-bit input dan 16-bit output. Proses perhitungan melibatkan Finite State machine (FSM) untuk menghemat resource yang diperlukan. Proses verifikasi sistem dilakukan dalam dua tahap, yaitu verifikasi fungsional dengan aplikasi ModelSim-Altera dan verifikasi hardware menggunakan modul FPGA Cylcone IV EP4CE6E228N. Hasil verifikasi menunjukkan bahwa hasil perhitungan akar kuadrat memiliki resolusi sampai dengan 0,0039. Selain itu, sistem ini membutuhkan 157 Logic Elements dan 120 register dengan kecepatan clock tertinggi yang dicapainya adalah 205 MHz untuk input 32 bit



Square root computing is required in several control processes, such as for Direct Torque Control (DTC) on motor drive systems that require a very fast calculation process. Field Programmable Gate Array (FPGA) is one of the devices that recommended for high speed and precision computation. The implementation of the square root on the FPGA uses the digit-by-digit non-restoring method with some modifications to get a high precision of computation result. The system is implemented using 32-bit input and 16-bit output. The calculation process involves a Finite State machine (FSM) to minimize computation resources. The system verification process is carried out in two stages, i.e. functional verification using the ModelSim-Altera and hardware verification using the FPGA Cylcone IV EP4CE6E228N. The verification shows that the result of the square root calculation has a resolution of up to 0.0039. In addition, the system requires 157 Logic Elements and 120 registers with the highest clock speed can achieves 205 MHz for 32-bit input.


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Cara Mengutip

Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA). (2022). Jurnal Teknologi Informasi Dan Ilmu Komputer, 9(7), 1617-1622.